The main challenges of NAND Flash and other types of non-volatile memories are their higher cost relative to Hard-Disk-Drive memories, slow write time, limited endurance (defined as the maximum number of Program/Erase cycles) and limited high temperature data retention time. Furthermore, in order to improve cost parameters, one must use higher-density (more bits per cell) NAND Flash, which in turn degrades its endurance and data retention.
Manufacturers have addressed the endurance and data retention challenges by introducing codes with higher error-correction capability to protect the data. A higher error correction capability directly translates into an increase in endurance, since the memory can withstand more wear, while still allowing for the information to be retrieved. However, increasing the error correction capability of the code requires increasing the computational complexity of the decoder, resulting in a reduction of the read throughput and a significant increase in power consumption.
The invention described here is a novel information decoding scheme which lowers the power consumed by the decoder. The invention provides a more efficient decoding of the noisy read values, regardless of where the noise comes from. The disturbance mechanisms addressed by this invention include inter-cell interference, read disturbance, erratic over-programming, high temperature retention loss, low temperature retention loss, high number of Program/Erase (P/E) cycles, coarse (faster) write and coarse (faster) read operations.